Products > Fab Processes > IBM > IBM 0.18 Micron 7SF Process
7SF CMOS Process
IBM Semiconductor 0.18 Micron
This process is available on taxi and dedicated runs (also known as COT or Customer Owned Tooling). It is not listed on the MOSIS Multi-Project Wafer Run Schedule.
If your design will be used for production, i.e. non-MPW, please read the IBM policy described in "Checking and Error Disposition Strategy for IBM Designs." IBM considers taxi runs as MPW. Designs approved for fabrication on taxi runs may not pass the more stringent design checks required for IBM production runs.
Process Description
MOSIS is offering access to the IBM 0.18 micron logic CMOS 7SF technology for prototype and low volume fabrication. C4 (IBM's flip chip bumping) is subject to availability at additional cost. Advance notice required. Please submit your inquiry through the MOSIS Support System.This CMOS process has 6 metal layers (M1, M2, M3, M4, M5, LM) plus TV (transfer) to DV (glass cut).
7SF Supported Options
Please refer to the List of 7SF Supported Options page for the options available on MOSIS MPW runs in this technology. You may not submit a design containing any options or metals stack which are not listed here without prior arrangement with MOSIS. Other configurations are available for dedicated runs.
Design Considerations
To ensure that submitted data is on a 10 nm grid, please stream-out at 1 DBU = 10 nm (Cadence 0.010, not 0.001).
MOSIS does not fill for IBM processes. Designs for IBM runs must meet the IBM fill requirements when submitted.
IBM Design Rules, Process Specifications, SPICE Parameters, and Cell Libraries
IBM has sub-licensed MOSIS to distribute this information to customers who have signed both the MOSIS customer agreement and the IBM Design Kit License Agreement.The CAD tool support files, DRC and LVS decks, simulation files, cell libraries, and files listed on the IBM CMOS Design Kits page are the only kits and files available.
Design rules supported by this technology
Only the IBM design rules will be supported for this technology.
MOSIS Technology Codes
The technology code for the 7SF process is IBM_7SF.
Parametric Test Results and SPICE Model Parameters
See Test Results for IBM 0.18 nanometer runsReticle/Wafer Size, Steps, Die and Wafer Thickness
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IBM CMOS
0.18 Micron 7SF Process |
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Wafer Size
(inches) |
Reticle Size (milli- meters, approx.) | Reticle Copies Stepped on Wafer (approx.) |
Die Thickness (+/- .5 mil) |
Bumped Die Thickness **
(+/- .5 mil) |
Wafer Thickness | ||||
| Mils | Micro- meters | Mils | Micro- meters | Mils | Micro- meters | ||||
| 8 | 18 x 20 | 60 | 10 | 250 | 10 | 250 | 30 | 760 | |
** Die thickness only. Does not include height of the bumps.
To order a special bumped die thickness, describe your requirements in the SPECIAL-HANDLING parameter of your New Project, Fabrication, or Update Request.